The disclosure of U.S. Provisional Patent Applications Ser. No. 60/291,348, filed May 15, 2001; 60/303,695, filed Jul. 6, 2001; 60/304,387, filed Jul. 9, 2001; 60/335,021, filed Oct. 31, 2001; and 60/365,599, filed Mar. 18, 2002, are hereby incorporated herein by reference in their entireties. This application is related to U.S. patent application Ser. Nos. 09/658,259, filed Sep. 8, 2000; 60/300,129, filed Jun. 22, 2001; and Ser. No. 10/099,523, filed Mar. 15, 2002, the disclosures of which are hereby incorporated herein by reference in their entireties.
Applications that require manipulation of many optical signals are becoming more complex and more commonplace. Such applications include the routing of signals in fiber optic networks, necessitated by, for example, telecommunications and large volumes of internet data traffic. Large volumes of signals must be processed, transmitted to or received from optical fibers, where the optical fibers are typically present as arrays of up to 100×100 fibers; larger arrays are possible and may be expected in the near future. As these optical interconnection networks become more complex and the volume of signal traffic increases, it becomes more and more important to reduce signal loss and cross-talk and to minimize the size of the optical/optoelectronic interconnect package.
Integration of Electronic, Optoelectronic and Optical Functions
The optoelectronic devices that perform optical signal processing tasks, for example, lasers, light-emitting diodes, photodetectors, photomodulators and the like, must be efficiently interfaced with the optical fibers or waveguides used in high speed telecommunications and data networks. Additionally, in an optical communications system, the optical signals are converted to electrical signals, and vice versa. Increasing the integration of the electrical functions with the optoelectronic functions has the potential to increase speed and reduce losses.
A desirable optical/optoelectronic interconnect package will provide high signal-to-noise ratio and high speed; low parasitic capacitance and inductance; high density; low crosstalk between devices; and low power consumption. A desirable optical/optoelectronic interconnect package will allow integration of multiple electrical functions such as driver circuits, signal processing circuits, input/output functions. Furthermore, the optical/optoelectronic interconnect package will enable efficient alignment of optical fibers with optoelectronic devices. Yet further, the optical/optoelectronic interconnect package will be capable of being economically manufactured and tested.
Optical/Optoelectronic Integration
In high speed telecommunications and data networks, the optoelectronic devices must efficiently transmit optical signals to and receive optical signals from the optical transmission grid, that is, optical fibers or waveguides. Optical fibers have an optical core that transmits light and an outer cladding layer that has a lower refractive index than the optical core. Optical fibers used in networks may be multi-mode or single mode, depending on the size of the optical core, and are selected based on the distance over which the optical signal needs to be transmitted and the bandwidth desired. Optical fibers are formed from a variety of materials such as glasses and plastics, glasses being predominant. It is understood that the optical signals are transmitted in the optical core along the fiber's long axis, and at the fiber's end the signals are emitted and received by the optical fiber's optical core, though for shorthand convenience, signal transmission is sometimes said to be by “the optical fiber.”
Individual fibers or arrays of fibers may optically connect with an individual optoelectronic (OE) device or an array of OE devices in a one-fiber/one-OE-device relationship, or the fibers may be present as bundles of fibers where a plurality of fibers optically interface with one OE device. Effective coupling between OE device and optical fiber requires precise alignment. A low-loss optical pathway must be defined between the optical fiber core(s) and the active region of the optoelectronic device.
The optical fiber arrays with which the optoelectronic devices must couple are often mounted in fiber optic connectors (ferrules), which are housings that (a) position the fibers in a precisely specified and fixed spaced-apart relationship to each other, and (b) provide means to align and mount the fiber array so that it will mate precisely with an array of optoelectronic devices or another array of optical fibers. Designs for these optical ferrules are increasingly becoming standardized. An example of such a standard optical fiber connector is the “MT” (mechanically transferable) ferrule, which precisely positions an array of optical fibers in a V-groove substrate and provides alignment means in the form of guide holes whose position relative to the fibers is tightly specified. The alignment means employ complementary mechanical alignment members in the form of guide pins.
Therefore a desirable optical/optoelectronic interconnect package and packaging method will facilitate precise alignment and mating with optical fiber ferrules, V-groove substrates, or connectors. The alignment process should position the active areas of the optoelectronic devices in registration with the fiber optic cores with high precision.
U.S. Pat. No. 6,130,979 describes an optoelectronic module having laser diodes mounted on a metal lead-frame structure in an arrangement that corresponds to the position of optical fibers mounted in an optical fiber ferrule. The metal lead frame has a pair of holes for receiving guide pins that are used to align the lead frame to the optical fiber ferrule. Electrical circuitry for driving or controlling the laser diodes is not provided within this structure.
For electrical connection with electrical circuitry for driving or controlling the devices, optoelectronic devices such as vertical cavity surface emitting lasers (VCSELs) typically have two electrical leads. At least one connection is made to the top side of the device, that is the side that bears the optically active (light emitting, light detecting, light modulating, etc.) region. VCSELs typically have a top electrical contact, and the second electrical contact may be made to the opposite (bottom) side, although it is anticipated that newer, faster devices that have both electrical contacts on the top side will increasingly be preferred. Therefore, space constraints figure strongly in the design of packages that integrate electronic functions with optoelectronic devices.
The requirement to make electrical contact to the optoelectronic device on the same side as the region to which light must have access makes it difficult to efficiently configure the light path between the optical fiber and the optoelectronic device, taking into account the need for high speed electronic circuitry for driver or amplifier, control, and I/O functions. This high speed electronic circuitry is typically fabricated on a separate integrated circuit chip. The high speed electronic circuitry is typically formed in silicon, most preferably as CMOS circuitry, but may comprise other device types and can be formed in other materials such as SiGe or InPbP. Because of these constraints, wire bonds are typically used to connect a bonding pad associated with each optoelectronic device with a corresponding bonding pad on the separate integrated circuit chip.
For example, a parallel fiber optic/optoelectronic link designed for high volume use in telecom and datacom switches was recently described by Rosenberg et al. (“The PONI-1 Parallel-Optical Link,” 49th Electronic Components and Technology Conference, San Diego, Calif. Jun. 1-4, 1999; U.S. Pat. No. 6,137,929). In this system, which constitutes a link between 1×12 arrays of VCSELs and optical fibers, the VCSEL driver circuitry on a silicon integrated circuit chip is wire bonded to the optoelectronic devices; a 1×12 array of OE devices requires 12 wire bonds. A wire bond is required to make a top contact to each VCSEL, necessitating a certain amount of clearance around each VCSEL. The end surfaces of the optical fibers are flush with or extend slightly beyond casing of the optical fiber ferrule (e.g. MT ferrule). Because of the space required for the wire bond, the optical fiber end surfaces cannot be brought flush with or sufficiently close to the optoelectronic devices to make a low-loss optical connection. An optical cover or “faceplate” system is used to transmit light more efficiently between the optical fiber core and the optoelectronic device.
European Patent Application EP 1028341 A2 (by Giboney, Rosenberg, and Yuen) describes a fiber optic-optoelectronic alignment system for use with this type of connector. The alignment system features a printed circuit board which is attached to a mechanical support. The printed circuit board has cutouts or access holes concentric with alignment holes in the mechanical support. Optoelectronic devices are positioned on the printed circuit board, which is then positioned on the mechanical support. Optical fibers in an optical fiber connector that has corresponding alignment holes can be aligned with the mechanical support by means of complementary guide pins. The optical fiber connector and hence the optical fiber ends are separated from and stand off from the optoelectronic devices with a cover positioned in between. The cover has corresponding guide holes through which the guide pins pass and a light-transmissive window through which the optical signals are transmitted.
Wire bonds are often the most physically fragile part of an electronic package. Furthermore, wire bonds introduce parasitic resistance, capacitance and inductance hence increased power dissipation. Krishnamoorthy et al. analyzed the issues involved with integrating optoelectronic components with silicon controlling circuitry, in particular the performance penalty imposed by wire-bonding optoelectronic components rather than flip-chipping (“Optoelectronic-VLSI: Photonics Integrated with VLSI Circuits,” IEEE Journal of Selected Topics in Quantum Electronics, Vol. 4, No. 6, November/December 1998, pages 899-912). Their analysis modeled maximum transmission (bit rate) for given power dissipation. Even for relatively low numbers of integrated optoelectronic devices, wire bonding imposed severe penalties on bandwidth and power dissipation.
To avoid these deleterious electrical and mechanical effects and to enable a low-loss optical pathway to be formed more simply between optical fiber and optoelectronic device, it is desirable to minimize the number of wire bonds that are present in an optical communications package. Hence an optoelectronic/optical coupling method that avoided or minimized the number of wire bonds would be desirable.
Electronic/Optoelectronic Integration
Therefore, it is also necessary to combine high density, high speed controlling electronic circuitry (most advantageously fabricated in silicon) with the optoelectronic devices in an intimate fashion that minimizes parasitic capacitance and inductance. More closely integrating the electrical circuits with the optoelectronic devices has the potential to increase speed and reduce losses, but close integration must not lead to excessive heat transfer from the electrical circuits to relatively heat-sensitive OE devices and consequent performance degradation.
At the wavelengths of interest in optical networks, in the visible to infrared ranges, optoelectronic devices (for example, lasers, photodetectors, photomodulators and the like), are typically made by epitaxial processes or monolithically in optically active materials, such as compound semiconductors, most commonly III-V materials, especially GaAs, as well as II-VI semiconductors such as ZnSe, transparent ferroelectrics such as lithium niobate and other related oxide materials, and liquid crystal and other optoelectronic polymers. For example, vertical cavity surface emitting lasers (VCSELs) are typically fabricated in AlGaAs and GaAs on GaAs substrates; photodetectors may be made in various III-V materials such as InP.
The controlling circuitry for the optical/optoelectronic coupling system is most advantageously formed in silicon. Silicon-based metal-oxide semiconductor (MOS) technology is virtually the standard for digital circuits that are used for to control the signal processing tasks in switching systems. No other approach can compare with the high device densities and high yields available with silicon CMOS (complementary MOS) technology, and standard silicon integrated circuit processing technology is so well-developed that it would be desirable to employ standard IC processing steps for the fabrication optical/optoelectronic coupling system to the greatest extent possible. Closely integrating the CMOS circuitry with the optoelectronic devices while minimizing the need for wire bonding could greatly increase both the performance and production efficiency of overall optical/optoelectronic signal processing package.
To date, various methods to integrate electronic and optoelectronic functions have been tried, with less than ideal results. Heteroepitaxial growth of GaAs on silicon, and silicon on GaAs have been explored, but after decades of research, fundamental problems such as the mismatch in the crystal lattice constants, cross-contamination, incompatibilities of device processing, and the difference in the coefficients of thermal expansion of the two materials have prevented this goal from being satisfactorily achieved on a commercial scale, particularly when high performance lasers, photodetectors or drive electronics are required. Epoxy casting, by which completely fabricated chips are mounted in a common epoxy cast and final metal deposited (multi-chip modules) has numerous problems, including high cost and poor parasitics, size, reliability and yield.
Flip-chip bonding is a packaging technique of mounting the active side of a chip toward a substrate. This technique, by which a chip is flipped over and attached to a substrate or other chip by a fusible joint, brings two dissimilar chips into intimate electrical and mechanical contact with each other and can reduce parasitics and improve speed. Commercial machines can perform this operation with great reliability and repeatability. Low temperature infrared (IR) detector arrays have been flip-chipped with silicon readout circuitry; the silicon substrate is transparent to the infrared wavelengths being detected by the IR detector array enabling a simple configuration. However, for the optical wavelengths used in current fiber optic networks, i.e., less than approximately 1 μm and typically about 850 nm, silicon is opaque and hence the substrate needs to be removed by etching or other means to provide optical access to the OE devices. Selectively etching optical access areas to provide light paths to an array of OE devices is a demanding and unattractive manufacturing step.
Furthermore, infrared detectors are generally low speed systems, often operating at Kilohertz speeds. For such low speeds, the parasitic effects of a bulk silicon substrate are virtually non-existent. However, optical communications systems operate at Gigahertz rates, or a million times higher in frequency. These high speeds cause the silicon substrate parasitics to become significant in areas of power consumption, crosstalk, distortion, maximum frequency and noise. These electrical limitations of silicon as a substrate material are true for all wavelengths of light being used. Therefore, even if the silicon is transparent at a given wavelength, it is not an ideal substrate for high speed (multi-Gigahertz) optical communication systems.
Manufacturing Considerations
As link data rates increase, optical links replace electrical links at shorter link distances, including applications such as bus architectures that require large numbers of links. Optical data links combining electronic circuitry, light sources and detectors, and optical fiber receptacles require high volume, low cost manufacturing techniques. Low cost, highly automated manufacturing and testing techniques are well known and available in the electronics industry for packaging components such as electronic integrated circuit chips on printed circuit boards. These techniques can be characterized as “planar” in that the components are affixed, electrically interconnected, and encapsulated on the flat surface of the printed circuit board.
However, these highly automated and precise methods have not heretofore been applied to assembling structures that incorporate integrated circuit chips and optoelectronic devices, packaged in a form that allows for the optoelectronic devices to be readily aligned to optical fibers for forming optical interconnections. The need to provide light access to the optoelectronic devices as well as electrical connections to separate integrated circuit chips has constrained the geometries of such packages. During manufacturing, complex manipulations in three dimensions are required, and the low cost automated assembly and testing techniques are not applicable to all the steps involved in assembling and packaging all the components of an optical data link. Alignment of the optoelectronic device and optical fiber may be a manual or relatively expensive hybrid manufacturing step.
Furthermore, current methods of packaging optoelectronic devices with the associated integrated circuits used for control of the optoelectronic devices do not allow for handling, test and burn-in at the chip scale package level. The optoelectronic devices cannot be “burned in” (stressed at conditions that are designed to simulate extreme conditions the product may encounter and provoke any failures that could occur) and tested under operating conditions until a late stage of manufacturing. Burn-in and test at a late stage, when the components—optoelectronic device die, integrated circuit die, alignment means—have been mounted and assembled into a module, results in yield loss of fully packaged components, leading to overall higher costs.
There is therefore a need for an optical coupling and alignment method that can be used in packaging designs that allow the optoelectronic devices and the associated integrated circuit chips to be tested at an earlier stage, prior to optical data link module assembly. Such packaging designs should be capable of being manufactured by highly automated, low cost manufacturing techniques, preferably using planar manufacturing methods that are well known and have become highly developed in the electronics industry.
Further, a desirable optical coupling and alignment method will enable optical/optoelectronic interconnect packaging designs that have a reduced number of tightly specified or demanding manufacturing steps; have fewer failure-susceptible parts such as wire bonds; and generate a smaller amount of waste heat and/or effectively route waste heat away from heat-sensitive optoelectronic devices. Such optical/optoelectronic interconnect packages may also need to meet multiple standards, such as precisely specified regular spacing between optoelectronic device active areas or between optical fiber cores (e.g., 250 μm pitch); physical dimensions of the optical connections; and reliability characteristics including thermal cycling, humidity resistance and mechanical durability.
In addition, a desirable optical coupling and alignment method will provide an optical/optoelectronic interconnect package capable of being manufactured in an array format for processing optical signals between arrays of optoelectronic devices and arrays of optical fibers. Optical fibers are often provided in 1×12 arrays or “ribbons”, although much larger one- and two-dimensional fiber arrays are in development and coming into use. The array sizes can be expected to grow as networks become more complex. Hence a useful packaging system will be configured to handle arrays in a simple and scalable fashion. Networks are increasing in both speed and number of connections in response to increasing data bandwidth demand. As networks increase in size, the number of nodes increases exponentially, because of the requirements to make connections between multiple systems; to provide backup and storage functions; to provide redundant paths, and to allow flexible system operation.